1. Field of the Invention
The present invention relates to a method of forming devices having three different operation voltages, and more particularly, to a method of forming HV devices, MV devices, and LV devices where the MV devices and the LV devices are able to be unaffected under operations of the HV devices.
2. Description of the Prior Art
Due to the advantages of low cost and tiny size, the concept of system on chip (SOC) has been progressively developed. Although integration of different devices, such as HV devices, LV devices, and memory devices, is beneficial in many aspects, there still exists difficulties in integrating different devices. Currently, HV devices and LV devices (i.e. 18V/3.3V) or MV devices and LV devices (i.e. 5V/3.3V) have been integrated. Please refer to FIG. 1. FIG. 1 is a schematic diagram illustrating LV devices and HV devices integrated in a substrate. As shown in FIG. 1, the substrate 10 is classified into an LV region 12, and an HV region 14. The substrate includes an LVPMOS device 16 and an LVNMOS device 18 respectively positioned on an n well 20 and a p well 22 in the LV region 12, and an HVPMOS device 24 and an HVNMOS device 26 respectively positioned on an n well 28 and a p well 30 in the HV region 14. In addition, all MOS devices are isolated by field oxide layers 32.
The conventional integration of HVMOS and LVMOS, however, suffers the following issues. First, due to insufficient isolations, the LVMOS may be affected during operations of the HVMOS, particularly when the HVMOS operates in a high positive voltage and in a high negative voltage. In addition, since only HVMOS and LVMOS (or MVMOS) are integrated, the application is limited.